Starting from the second half of 2020, various mobile phone chip manufacturers have begun a fierce competition for 5nm chips. Apple, Huawei, Qualcomm , Samsung has successively launched flagship 5nm mobile processors, and claimed to have excellent performance in terms of performance and power consumption.

However, judging from the actual performance of these 5nm chips, some users did not buy it, believing that the performance of 5nm mobile phone chips did not meet expectations, and that 5nm chips seemed to have suffered a collective”rollover.”

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5nm chips collectively”turn over”, the embarrassment from 7nm to 5nm

The first commercial 5nm chip was the A14 on the iPhone12 series in October last year. Bionic chip, this chip transistor reached 11.8 billion, nearly 40%more than A13, and 6-core CPU and 4-core GPU use Its CPU performance is increased by 40%, graphics performance is increased by 30%, and power consumption is reduced by 30%.

Followingly, Huawei released the Kirin 9000, which integrates 15.3 billion transistors, 8-core CPU, 24-core GPU and NPU AI processor. Officially, its CPU performance is increased by 25%and GPU is increased by 50%.

In December, Qualcomm and Samsung released the Snapdragon888 and Exynos which were manufactured by Samsung. 1080, also claimed that the performance has been greatly improved, and the power consumption has decreased.

The first suspected”rollover” was revealed to be the A14.

According to a foreign media 9to5Mac report, some iPhone 12 users encountered high power consumption problems when using their mobile phones. The power consumption dropped by 20%to 40%overnight in standby mode, whether it was during the day or night, whether it was turned on or not. Many background programs, the result remains the same.

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The most widely criticized by users is Snapdragon 888.

In the test of the first batch of users, many digital review bloggers pointed out that the performance improvement of Xiaomi Mi 11, which first released the Snapdragon 888, is limited, and the power consumption is directly increased. Some people attribute this to the immaturity of Samsung’s 5nm process, the foundry of Snapdragon 888. Since then, Samsung’s own two 5nm chips are also facing the risk of”rollover”.

According to Moore’s Law, the number of transistors in a chip doubles every 18 months, and the performance will also double. However, it is becoming more and more difficult to scale transistors. Nowadays, it is changing from 7nm to 5nm. In the process of advancement, the performance of mobile phone chips seems to be unsatisfactory, not only limited in performance improvement, but also in power consumption, facing the embarrassment of advanced process cost-effectiveness.

Why are 5nm chips overturning frequently? How does the performance and power consumption change when the chip process is more advanced?

Performance is prioritized during design, and the process is immature during manufacturing

The power consumption of integrated circuits can be divided into dynamic power consumption and static power consumption.

Dynamic power consumption is easy to understand. It refers to the power consumption generated when the circuit state changes. The calculation method is similar to that of ordinary circuits. According to the physical formula P=UI, dynamic power consumption is affected by voltage and current.

Static power consumption is the power consumption of each MOS tube leakage current, even though each MOS tube generates The leakage current is small, but because a chip often integrates hundreds of millions or even tens of billions of transistors, the overall static power consumption of the chip is relatively large.

During the development of the chip technology process, when the process technology is not too advanced, the dynamic power consumption accounts for a large proportion. The industry has abandoned the original 5V fixed voltage design model and adopted a proportional reduction Pressure slows down the growth rate of power consumption.

However, the reduction in voltage also means that the switching of transistors will become slower. Some manufacturers that pay more attention to performance, even if they use more advanced technology, they still maintain the 5V supply voltage, which ultimately leads to Increase in consumption.

With the progress of process nodes, the importance of static power consumption gradually appears. From the chip process development of Intel and IBM, it can be seen that in the process of process evolution from 180nm to 45nm, transistor integration has increased With different speeds, dynamic power consumption may increase or decrease, but static power consumption has been on the rise. At 45nm, static power consumption is almost the same as dynamic power consumption.

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Although some design manufacturers would rather make sacrifices to reduce power consumption and improve performance, they have to face the negative impact of high power consumption.

For users, severe heat generation and severe power consumption of the device are a direct impact of high power consumption. If the heat dissipation of the chip is not good, it will cause the chip to be abnormal or even fail in severe cases.

Therefore, the industry still regards low-power design as one of the problems that the chip industry needs to solve. How to balance the performance, power consumption and area (PPA) of the chip under the advanced node is also chip design and manufacturing Challenges.

In theory, the more advanced the chip manufacturing process, the lower the power supply voltage will produce lower dynamic power consumption. As the process size is further reduced, the chip voltage that has dropped to 0.13V is difficult to further decrease , So that when the process size is further reduced in recent years, the dynamic power consumption basically cannot be further reduced.

In terms of static power consumption, the channel parasitic resistance of the field effect transistor becomes smaller as the node progresses. When the current is constant, the power of a single FET also becomes smaller. But on the other hand, the double-speed increase in the number of transistors per unit area increases static power consumption, so the final static power consumption per unit area may remain unchanged.

In pursuit of lower costs, manufacturers use smaller-area chips to carry more transistors. It seems that the more advanced the process, the better the chip performance and the lower the power consumption. However, the actual situation is often much more complicated. In order to improve the overall performance of the chip, some people increase the core, and some people design more complex circuits. Following this, more paths stimulate power consumption growth, and new methods are needed to balance power consumption.

FinFET, which has a significant impact on the chip industry, is one of the ways to balance chip performance and power consumption. Through a fin-like structure to control the connection and disconnection of circuits, circuit control is improved and leakage current is reduced. The channel of the transistor is also greatly shortened, and the static power consumption is reduced accordingly.

However, the evolution from 7nm to 5nm is more complicated.

Moortec Chief Technology Officer Oliver King once said in an interview with foreign media:”When we upgrade to 16nm or 14nm, the processor speed has been greatly improved, and the leakage current has also dropped. Faster, so that we can do more things with limited power when using the processor. But when the process from 7nm to 5nm, the leakage situation becomes serious again, almost the same level as 28nm, now we have to go Balance them.”

Cadence’s digital and approval group senior product management director Kam Kittrell also said,”Many people have not figured out what can consume so much power. They need to advance Obtaining workload information can optimize dynamic power consumption. For a long time, we have been focusing on static power consumption, so that once switching to the FinFET node, dynamic power consumption becomes a big problem. In addition, the emergence of multiple cores may also overload the system. Therefore, there must be a smarter solution.”

This is a common problem faced by 5nm chip design and manufacturing companies, so it is possible to understand a little why the existing 5nm chips collectively”turn over.” Immature design and manufacturing will affect the maximum trade-off between performance and power consumption. Of course, it is not ruled out that chip design manufacturers are unwilling to make great efforts to reduce power consumption in pursuit of better performance chips.

The embarrassing thing is that the more advanced the process, the greater the capital investment required. In fact, there are not many fields pursuing advanced processes such as 7nm and 5nm. If the advanced process cannot be used in power consumption and performance There is a great improvement in the above, then the pursuit of a more advanced process does not seem to have the original meaning.

Are you really ready to move towards 3nm?

According to the data given by the market research organization International Business Strategies (IBS), the design cost for the 65nm process only needs 24 million U.S. dollars, and the 28nm process requires 62.9 million U.S. dollars, 7nm and The cost of 5nm is increasing rapidly, and the cost of 5nm design reaches 476 million US dollars.

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At the same time, according to two authors from the Center for Security and Emerging Technologies (CSET) of the Walsh Diplomatic School of Georgetown University, a paper entitled”AI Chips:What They Are and Why They Matter” In the report, the author estimated with the help of models that TSMC’s charge for each 5nm wafer may be approximately US$17,000, nearly twice that of 7nm.

In the estimated model, the author estimates that each 5nm chip requires a manufacturing cost of $238, a design cost of $108, and a packaging and test cost of $80. This allows chip design companies to pay as high as US$426 (approximately 2939 yuan) for the total cost of each 5nm chip.

This means that whether it is a chip designer or a chip manufacturer, following Moore’s Law to develop advanced processes to 5nm and below, in addition to breaking the technical bottleneck, it also requires huge capital. As a support, survive the R&D cycle and test cycle, and provide the market with chips with improved power consumption and performance, and finally enter the payback period.

Therefore, not everyone in the industry is positive and optimistic about the advancement of 5nm chips. Amin Shokrollahi, CEO of chip IP supplier Kandou, said in an interview with foreign media:“For us, going from 7nm to 5nm is annoying. The circuit will not be scaled and it will cost a lot. Seeing the advantages of this. But customers want us to do this, so we have to do it.”

There is also Global Foundries, the world’s second largest chip foundry, which announced its shelving in 2018 due to economic considerations. The 7nm project will return resources to 12nm/14nm. Even the powerful Intel has been blocked many times during the development of 10nm and 7nm.

However, this still cannot stop the competition of various mobile phone chip design manufacturers in advanced manufacturing processes, and it cannot stop the battle for process supremacy between Samsung and TSMC.

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Previously, Leifeng.com reported that Samsung regards TSMC as its biggest competitor in advanced-process chip manufacturing. In the competition with TSMC, Samsung’s advancement of advanced processes has been intermittent. 7nm jumped to 7nm LPP EUV, both of which will achieve mass production of 5nm FF EUV in 2020, and now both have invested heavily in 3nm R&D and mass production.

Last Friday, TSMC CEO Wei Zhejia announced at an investor meeting that TSMC’s capital expenditure in 2021 will be as high as 25 billion to 28 billion US dollars, 80%of which will be used in 3nm, 5nm And for the advanced 7nm process, 10%is used for high-end packaging and masking, and the other 10%is used for special manufacturing processes.

According to the progress of TSMC’s 3nm process, it is expected to start trial production in 2021 and enter mass production in the second half of 2022 to help Intel foundry 3nm processor chips.

At the same time, Samsung has also stated that the cost of its 3nm GAA may exceed 500 million U.S. dollars, and is expected to use GAAFET 3nm process chips that are more advanced than FinFET in mass production in 2022.

Returning to the actual situation of 5nm mobile processors, no matter which manufacturer’s design and production, they are facing performance and power consumption problems. 5nm chips seem to be immature, and 3nm mass production is necessary Trial production will begin this year. 3nm, which is getting closer to the limit of Moore’s Law, is it really ready?

The cover image is from Alibaba Cloud

Reference source for this article:

https://www.leiphone.com/news/202009/ft8Mx9l2A1T3kCru.html

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Power And Performance Optimization At 7/5/3nm

http://www.paper.edu.cn/scholar/showpdf/MUT2EN1IOTD0Mx3h

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